![]() Due to parameter fluctuations in scaled technologies, stable operation is critical to obtain high yield low-voltage, low-power SRAM. Lowering power consumption and increasing noise margin have become two central topics in every state of the art SRAM design. Furthermore, the bitline leakage power consumption of the proposed 9T SRAM cell is reduced by up to 79\%, 76\% and 39\% when compared to the previously published 8T, 10T and 9T SRAM cells, respectively. With the proposed 9T SRAM circuit, the read static noise margin is nearly twice that of conventional 6T SRAM circuit. In this paper, we propose a novel 9T SRAM cell topology which achieves both cell stability as well as prevents bit-line leakage. These designs improve the cell stability in the subthreshold regime but suffer from bit-line leakage noise, placing constraints on the number of cells shared by each bitline. To overcome these challenges, researchers have proposed different topologies for SRAMs with single-ended 8T, 9T, 10T bitcell designs. ![]() ![]() These issues oppose our ability to achieve stable bitcells and acceptable performance while maintaining density using the standard six-transistor(6T) circuit. Nanoscale SRAM memory design has become increasingly challenging due to the reducing noise margins and increased sensitivity to threshold voltage variations.
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